In order to design an integrated circuit (IC), an integrated circuit designer must first provide a library of computer stored circuit cells and a behavioral circuit model describing the functionality of the integrated circuit. FIG. 1 illustrates a widely used and well known method for generating a library of computer stored logic cells. First, the integrated circuit designer needs to determine what cells are needed for the integrated circuit via a step 10. In this step, the human IC designer makes a human determination as to what logic cells are need to manufacture an integrated circuit. These cells typically include fundamental logic gates such as OR, NAND, NOR, AND, XOR, inverter, and like logic cells with an array of logic gate sizes. Once all the required cells are determined via step 10, a step 12 is performed. In the step 12, the IC designer hand-lays out the cells determined in step 10 via a computer graphical interface. In other words, the integrated circuit designer determines physical placement of transistors within each logic cell and determines conductive routing between electrodes of the transistors to form the required logic gates. Once this placing is determined by the human IC designer, the IC designer uses the graphical interface to enter these human determined positions into a computer data base in a two-dimensional format.
Step 14 in FIG. 1 is then used to verify the logic cells defined by the IC designer in step 12. In many cases, Step 14 will discover that the IC designer improperly connected or improperly placed a physical item within one or more cells. In this case, these errors are flagged to the IC designer so that the layout cells may be fixed so that the layout cells perform their proper logical operation. After the step 14, a step 16 checks the hand-laid-out cells to determine if a plurality of design rules are adhered to. Design rules are provided to integrated circuit designers to ensure that a part can be manufactured with greater yield. Most design rules include hundreds of parameters and, for example, include pitch between metal lines, spacing between diffusion regions in the substrate, sizes of conductive regions to ensure proper contacting without electrical short circuiting, minimum widths of conductive regions, pad sizes, and the like. If in step 16 a design rules violation is identified, this violation is flagged to the IC designer so that the IC designer can properly correct the cells so that the cells are in accordance with the design rules. After step 16, a step 18 is performed. In step 18, device physics parasitics are extracted from each of the library cells generated in steps 10-16 by the human IC designer. Parasitic quantities extracted include resistances, capacitances, impedances, inductance, and other like parameters which physically affect or are physically brought about by the cells designed in steps 10-16. In a step 20, the parameters extracted from step 18 along with the physical two dimensional layout of cells defined in steps 10-16 is used to characterize the cells for use in integrated circuit design. When designing an integrated circuit, it is important to take into account characterizations of the cells in order to ensure a functional integrated circuit. The characterizations are found in step 20 and typically include signal rise time, signal fall time, power consumption, propagation delay times though the device, area of the cell, skew rates, and other parameters which may be applicable to the logic cells. Once steps 10-20 have been performed, a library of unconnected cells having inputs and outputs have been adequately formed for use in integrated circuit design. The cells are used as building blocks which are pieced together into a larger interconnected cell-structure known as an integrated circuit.
Once a library is formed via FIG. 1, the library is used in a step 22 of FIG. 2 to design an integrated circuit from the cells defined in FIG. 1. The human IC designer presents as input to a logic synthesis tool 26, the library of cells from step 22 (see FIG. 1) a behavioral model from step 24 in FIG. 2. The library of cells of step 22 was discussed in detail in FIG. 1. The behavioral circuit model is typically a file in memory which looks very similar to a computer program. The behavioral circuit model contains instructions which define logically the operation of the integrated circuit. The logic synthesis tool of step 26, receives as input the instructions from the behavioral circuit model and the library cells from the library in step 22. The synthesis tool 26 maps the instructions from the behavioral circuit model to one or more logic cells from the library to transform the behavioral circuit model to a gate schematic net list of interconnected cells. A gate schematic net list is a data base having interconnected logic cells which perform a logical function in accordance with the behavioral circuit model instructions. In the prior art, once the gate schematic net list is formed, it is provided to a place and route tool via a step 28.
Even though the gate schematic net list contains the initial library cells interconnected into a data base to function in a manner analogous to the behavioral circuit model, the gate schematic net list does not indicate physical placement of cells on an integrated circuit substrate or dye. In other words, the cells in the gate schematic net lists are not physically positioned with respect to one another. The place and route tool of step 28 is used to access the gate schematic net list and the library cells of step 22 to position the cells of the gate schematic net list in a two-dimensional format within a surface area of an integrated circuit die perimeter. The output of the place and route step 28 is a two-dimensional physical design file which indicates the layout interconnection and two-dimensional IC physical arrangements of all gates/cells within the gate schematic net list.
One problem with the widely used process illustrated in FIG. 2 is that the library (step 22 and FIG. 1) is created and defined in a static manner before the process of steps 26 and 28 are performed. The library is never changed after the step 22 and is not customized for the integrated circuit as steps 26 and 28 precede. For this reason, the IC designers are limited to the logic gates implemented in step 22 when performing steps 26 and 28 regardless of whether these cells are appropriate or not. This results in an integrated circuit having time delay problems, power consumption problems, surface area problems, and yield reduction due to static and unchanging library cell availability. These libraries are difficult to create and it is typical that a single library may be used to design multiple ICs and thereby incorporate the above problems into many ICs within a family of products. Therefore, the need exists for a design process which is more interactive in terms of further defining and manipulating library cells throughout the entire design process.